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\efe Peizold United States Patent Ofilice 3,373,362 STATIC COUNTERINCORPORATING STAGES HAVING MAIN AND AUXILIARY STORES Dieter Petzold,Berlin-Neulrolln, Germany, assignor to LicentiaFatent-Verwaltungs-Gm.l).H., Frankfurt am Main, Germany Filed Apr. 5,1965, Ser. No. 445,565 Claims priority, application Germany, Apr. 3,1964,

4 Claims. ci. 328-41) ABSTRACT OF THE DISCLQSURE The present inventionrelates to a static counter and, more particularly, to a static counterof the type disclosed in my copending application Ser. No. 327,585,filed Nov. 29, 1963.

The counter shown in application Ser. No. 327,585, is a binary countercapable of counting forward or backward, which may be provided withmeans for converting the counter into a decimal counter, and which has aplurality of counter stages each incorporating two memory units, namely,a main storage device and an auxiliary storage device, termed main andauxiliary stores, respectively. The counter is controlled by means ofcounting signals and auxiliary counting signals which may have anysuitable wave shape, these counting signals and auxiliary countingsignals being time displaced, i.e., staggered with respect to each otherin the sense that they do not change their states (L or O, with L beingused to represent the binary one) simultaneously. The counter describedin application Ser. No. 327,585, has the counting signals applied inparallel to the main stores of all of the counter stages while theauxiliary counting signals are applied in parallel to the auxiliarystores of all of the counter stages. All that is required of thecounting signals and auxiliary counting signals is that they be ofsuflicient amplitude and duration. Furthermore, the timely staggeredcounting signals and auxiliary counting signals will generally appearwith time intervals between them, i.e., there will be a time intervalbetween a given counting signal t and the corresponding auxiliarycounting signal t Any faults or disturbances which cause any countingsignal or auxiliary counting signal repeatedly to appear or todisappear, as, for example, shocks resulting from mechanical contactingor by oscillations of the signal generator, will not cause the counterto produce an incorrect count.

One drawback of the counter described in application Ser. No. 327,585 isthat, under certain circumstances, one of the counting signals orauxiliary counting signals applied to the counter may have such a smallamplitude, and/or be of such short duration, that the counter will willnot properly process such signal. Since, as explained above, the signaltrains are applied in parallel to the main and auxiliary stores of thecounter stages, it may happen that one or more of the main or auxiliarystores will not properly respond to such signal, while the remainingmain or auxiliary stores do respond properly. That is to say, it may bethat a given signal may be just small enough, or just short enough, sothat some of the stores to which it is applied will not respond but thatothers will. Consequent- 3,373,362 Patented Mar. 12, 1968 ly, theappearance of such an inadequate signal will cause the counter to putout an incorrect count.

It is, therefore, the primary object of the present invention to providea way in which to overcome the above drawback and with this object inview, the present invention resides in a counter which is basically ofthe abovedescribed type in that it incorporates stages having main andauxiliary stores, of which the main store puts out the count of theparticular digit, but wherein, in contradistinction to the counterdescribed in application Ser. No. 327,585, the counting signals andauxiliary counting signals are applied to the main and auxiliary stores,respectively, of the lowest-order counter stage only. New countingsignals and auxiliary counting signals 7' T2, are then derived from theoutput signals of the main and auxiliary stores of the lowest-ordercounter stage, and these new signals are then applied in parallel to themain and auxiliary stores, respectively, of all higher-order counterstages. The counter will, of course, be so designed that the newcounting and auxiliary counting signals 7 T2 will unquestionably befully adequate, i.e., of suflicient amplitude and duration, to controlall of the higher-order stages.

Additional objects and advantages of the present invention will becomeapparent upon consideration of the following description when taken inconjunction with the accompanying drawings in which:

FIGURE 1 is a schematic circuit diagram showing the first four stages ofone embodiment of a counter according to the present invention, the samebeing a forward counting binary counter having non-identical counterstages.

FIGURE 2 is a schematic circuit diagram showing the first four stages ofanother embodiment of a counter according to the present invention, thesame being a forward counting counter having identical counter stages.

FIGURE 3 is a schematic circuit diagram showing the 0th decade of aforward counting counter, the same including four binary stages whichare not all identical to each other.

FIGURE 4 is a schematic circuit diagram showing the 0th decade of aforward counting counter, the same including four identical binarystages.

FIGURE 5 is a schematic circuit diagram showing the first four stages ofstill another embodiment of a counter according to the presentinvention, the same being a backward counting counter havingnon-identical counter stages.

FIGURE 6 is a schematic circuit diagram showing the first four stages ofyet another embodiment of a counter according to the present invention,the same being a backward counting counter having identical counterstages.

FIGURE 7 is a schematic circuit diagram showing the 0th decade of abackward counting counter, the same including four binary stages whichare different from each other.

FIGURE 8 is a schematic circuit diagram showing the 0th decade of abackward counting counter, the same including four identical binarystages.

FIGURES 9a and 9b are schematic circuit diagrams of arrangements forproducing the new counting signals 7'1 and auxiliary counting signalsT2.

FIGURES 10a, 10b, 100, 11a, 11b and 110 are schematic circuit diagramsof arrangements for producing compensating signals which make itpossible to provide the counter with identical counter stages, thesignals produced by the circuits of FIGURES 10a and 1% being used inconjunction with the counter of FIGURE 2, the signals produced by thecircuits of FIGURES 10a, 10b and being used in conjunction with thecounter of FIGURE 4, the signal produced by the circuits of FIG- URES11a and 11b being used in conjunction with the 3 counter of FIGURE 6,and the signals produced by the circuits of FIGURES 11a, 11b and llcbeing used in conjunction with the counter of FIGURE 8.

FIGURE 12 is a time plot showing various signals applied to and producedby the counters of FIGURES 1 and 2.

FIGURE 12a is a schematic circuit diagram of a natural binary codecounter of the type shown in application Serial No. 327,585, namely, acounter in which the counting signals and auxiliary counting signals t tare applied in parallel to all of the stages of the counter. Thiscounter, and its operation, are set forth to facilitate the explanationof the present invention.

FIGURES 13a, 13b, 13c and 13d are time plots showing the timedrelationship between various signals in the counter of FIGURE 12a.

FIGURES 14a, 14b, 14c and 14d are, respectively, schematic circuitdiagrams of means for producing signals used in the counter of FIGURE12a.

In each of the various circuit diagrams, the AND- circuits areidentified by & (in some cases with subscripts) and the OR-circuits byv, and in each case the black bar represents the presence of an inverseor complement, i.e., a negated, output. Various ones of the circuitsalso include pure inverter or so-called NOT- circuits, these beingcircuits at which the output is the inverse, that is to say, the negate,or complement, of the input, namely, when the input is L and L when theinput is O.

In the time plots, only the afiirmative signals are shown, in theinterests of simplicity and clarity. That is to say that, for example,only the signals I but not the negates 7 thereof, are shown. Also, thesignals are shown as having a rectangular wave form although in practicethe wave form need not necessarily be square. As a matter of expediency,the abscissa of each signal represents the value 0 while the linesoverlying the abscissa represent the binary one or L.

For purposes of explanation, reference will be made to the staticcounter shown in application Ser. No. 327,585, one embodiment of whichis depicted in FIGURE 12a of the accompanying drawings. FIGURE 12a showsthe first four counter stages of a binary counter made up of identicalcounter stages, each incorporating a main store S and an auxiliary storeS Each store is identified by an appropriate subscript, e.g., S 8 Thestores are constituted by input AND-circuits whose outputs are connectedto OR/NOT/NOT-circuits. All of the stores are galvanically coupled toeach other. The configuration or wave shape of the applied input signalsis of no consequence; all that is necessary is that the input signalshave certain predetermined amplitudes.

There will now be described the operation of the counters as well as thesignficance of the various signals.

The counter has applied to it the actual counting signals 1 as well asauxiliary counting signals t the signals t and t being staggered ortime-shifted with respect to each other, i.e., the signals t and t occurat different times and, as shown graphically in FIGURE 13a, there aretime intervals between the signals t and t The signals themselves, aswell as the time intervals therebetween, may be of different durations.If the timed relationship between the signals 2 and t; is as depicted inFIGURE 13b, t can be used as the counting signal and T as the auxiliarycounting signal. If the timed relationship between the signals t and Iis as shown in FIGURE 13c, two AND-circuits can be used for producingtwo signals (t & t and & t which are staggered with respect to eachother and between which there is a time interval. The repeateddisappearance and reappearance of the t-signalsas depicted in FIGURE 13dand as might be produced by shocks or vibrations to which the pulsegenerator is subjected-will not adversely influence the operation. Thesignal trains identified in FIGURE 13d at a, will each be considered, bythe counter, as one counting signal, comparable to the signals a, ofFIGURE 13a. The same applies to the signal trains 11 each of which willbe considered by the counter as an auxiliary counting signal.

The A-signals represent the number of counting signals t registered bythe counter. The H-signals are auxiliary signals which are formed by thecounter itself and which assist the function of the counter. Asexplained above, the A-signals and H-signals of the binary counter areidentified by subscripts. The signal A, (i=0, 1, 2, 3, of the binarycounter thus has the value 2 Before the start of a counting operation,the counter is put into a definite starting position by means of anerase or reset signal l=L. During the counting operation, the resetsignal 1:0. For purposes of simplification, those signals which in eachcounter stage together act on one AND-stage, are separately combined.The counters therefore have applied to them t'-signals which are derivedfrom the t-signals and the negated reset signal I by means of thecircuits shown in FIGURES 14a, 14b and 140. The e-signal produced by thecircuit of FIGURE 14d is provided solely so that the auxiliary store ofthe counter stage of the lowest order is constituted by circuitrysimilar to that of the auxiliary stores of the higher-order counterstages. The circuit shown in FIGURE 14d comprises two input AND-circuitswhose outputs are connected to an OR/NOT-circuit. One of theAND-circuits has applied to it the negate of a counting command signal zby means of which the counter is made to count (when z=L) or not tocount (when z=0). (The single-input AND-circuit just referred to, aswell as other single-input logic circuits which are part of circuitryreferred to throughout the following description, are provided forpurposes of electrical symmetry.) The other AND-circuit has applied toit the signals A and 1 The signal Z is derived from the z-signal, whichmay appear at any time, and a signal 22 is derived from the signal Zsuch that Z2 can change its state only at the start of an auxiliarycounting signal t;,, as explained in the mentioned application Ser. No.327,585. The signal Z serves as a clear-for-counting signal, i.e., the t-signals are counted only so long as z =L. So long as 2 :0, the counterremains at whatever count it has reached. The counter can be preset toany desired starting number by means of preset signals k, the same beingidentified by subscripts and superscripts in a manner analogous to thatin which the A and H signals are identified, as explained above. Thek-signals are accepted by the counter when a clear-for-presetting signalf=L. Since the f-signal disappears at the start of the countingoperation, a new number to which the counter may later be preset can bemade ready during the counting opera tion. If no presetting is required,the means by which the presetting is accomplished can be dispensed with.

Referring next to FIGURE 1, the same shows a forward counting binarycounter according to the present invention, whose lowest-order counterstage Z incorporating the main store S and the auxiliary store S is, inprinciple, similar to the corresponding stage of the correspondingcounter disclosed in application Ser. No. 327,585, in that the mainstore S has the counting signal t and its negate I; applied to it whilethe auxiliary store S has the auxiliary counting signal 1 and its negateT applied to it.

According to the present invention, new counting signals 7'1 and newauxiliary counting signals T2, as well as their respective negates arederived from the counter stage Z which new signals are applied inparallel to the stores of the higher-order counter stages Z Z Z Moreparticularly, the new -r-signals are derived from the outputs of themain and auxiliary stores of the lowest-order counter stage. Variousinputs of the counter stages are provided with two references; in FIG-URE 1, for example, a line 1 is referenced a, l. The correspondingsignals can be combined in separate AND- circuits. The same applies tothe other counters to be described.

FIGURE 9a shows an AND/NOT/NOT-circuit for producing the new countingsignals T1 and the correspon ing negatesT The circuit of FIGURE 9a hastwo inputs to which are applied, respectively, the negated output signalK of the main store of the lowest-order counter stage and the outputsignal H of the corresponding auxiliary store. The new auxiliarycounting signals 1- and their corresponding negates 1- are produced bythe AND/NOT/NOT-circuit shown in FIGURE 9b, which has two inputs towhich are applied, respectively, the output signal A of the main storeof the lowest-order counter stage and the negated output signal I l ofthe corresponding auxiliary store. The new counting signals andauxiliary counting signals T1, 7- are of longer duration than theoriginal input counting signals and auxiliary counting signals t t andappear but half as frequently as do the signals t.

If, now, an inadequate counting signal t or auxiliary counting signal tis produced by the signal generator (not shown), the same is appliedonly to the main or auxiliary store of the counter stage Z Such a signalcan have but one of two possible effects; either the counter stage Zwill respond properly and change its state, or it will not. It, then,such inadequate signal is picked up by the stage Z in the same way as anadequate or nonfaulted signal would be, the same will be processed bythe stage and the new counting signals 7- and auxiliary counting signalsT2 derived from the outputs of the stage Z will be routinely processedby all of the higher-order counter stages. If, on the other hand, thelowest-order counter stage Z does not respond to the inadequate signal,the output signals at A and H remain unchanged and consequently no newcounting signals and auxiliary counting signals will be produced. Thismeans that the higherorder stages will not be affected in any way.

While in the counter of FIGURE 1, the auxiliary stores S and 8 of thecounter stages Z and Z are not identical to the auxiliary stores 8 and Sof the counter stages Z Z the counter of FIGURE 2 is so constructed asto have identical counter stages, the counter of FIG- URE 2 being aforward counting binary counter whose first four counter stages areillustrated. In order to enable all of the counter stages to be made upof identical components, the auxiliary stores S and 8 have compensatingsignals e and e applied to them. These signals are derived in thecircuits shown in FIGURES 10a and 10b, respectively, the formercomprising two input AND- circuits & & and one OR/NOT-circuit v the AND-circuits having the signals t and K applied to them, as shown, and thecircuit of FIGURE b comprising an AND/NOT-circuit & which has thesignals T2 and K applied to it. With the counter being used inconjunction with the circuits of FIGURES 10a and 10b as well as those ofFIGURES 9a and 9b all of the counter stages can be identical to eachother, thereby allowing the use of modular components.

FIGURE 3 is a schematic circuit diagram showing the first four binarystages of the 0th stage of a forward counting decimal counter, whichputs out, as its count, a decimal number in binary coded form. As in thecase of the counter of FIGURE 1, from which the counter of FIGURE 3 isderived, only the lowest-order counter stage Z has the counting signalsand auxiliary counting signals t t applied to it. The new countingsignals and auxiliary counting signals 1 T2, are then derived from theoutputs of the main and auxiliary stores of the lowest-order counterstage and these signals are applied to the higherorder counter stages,in the manner described above.

FIGURE 4 is a schematic circuit diagram showing the first four binarystages of the 0th stage of another forward counting decimal counterwhich differs from those depicted in FIGURE 3 in that all of the counterstages are identical to each other. In order to make this possible, theauxiliary stores S and S have the compensating signals e e 2 applied tothem, the first and second of which are derived in the circuits shown inFIGURES 10a and 1012, as described above, the third being derived in thecircuit shown in FIGURE 10c which comprises an AND/NOT-circuit 8: towhich the signals 7'2 and K are applied.

FIGURE 5 is a schematic circuit diagram of a backward counting binarycounter having non-identical counter stages. As in the case of thecounters described above, only the main and auxiliary stores S and Shave the counting signals and auxiliary signals t t applied to them, theoutputs of these stores being used to derive the new counting signalsand auxiliary counting signals T1, T2, which are then applied inparallel to the main and auxiliary stores of the higher-order counterstages.

The counter shown in FIGURE 6 differs from that of FIGURE 5 in that thecounter stages are identical to each other. Accordingly, the auxiliarystores S and have the compensating signals 2 and 2 applied to them; thesignal e is formed in the circuit shown in FIGURE 1111 which comprisestwo input AND-circuits & and 8: whose outputs are connected to anOR/NOT-circuit v the input AND-circuits having the signals 5 t and Aapplied to them, as illustrated. The signal c is formed in the circuitshown in FIGURE 11b which comprises an AND/NOT-circuit 8: to which thesignals T and A are applied.

The counter shown in FIGURE 7 is the 0th decade of a backward countingdecimal counter, the same being based on the counter of FIGURE 6, sothat here, too, only the 0th counter stage will have the countingsignals and auxiliary counting signals t t applied to it, the newcounting signals and auxiliary counting signals 7- 1 which are appliedin parallel to the higher-order counter stages, being derived from theoutputs of the main and auxiliary stores of the lowest-order counterstage Z As is apparent from FIGURE 7, the counter stages are notidentical.

The counter of FIGURE 8 differs from that of FIG- URE 7 in that thecounter stages are identical, the auxiliary stores S S S having thecompensating signals 2 c e applied to them. The signals e and c arederived in the circuits show in FIGURES 11a and 1112, respectively, thesignal e being derived in the circuit shown in FIGURE 11c whichcomprises two input AND- circuits 8: and 8: whose outputs are connectedto an OR/NOT-circuit v The two input AND-circuits have the signals A vand H applied to them, as illustrated.

FIGURE 12 is a time plot showing the operation of the counters ofFIGURES l and 2. The signals A and H are set and erased in the samemanner as in the counters described in application Ser. No. 327,585,i.e., when, between any two auxiliary counting signals, there appears atleast one counting signal of adequate amplitude and duration, or when,between any two counting signals, there appears at least one auxiliarycounting signal of adequate amplitude and duration. The time plot linesbracketed by (a) represent the case where it is assumed that all of theapplied counting signals and auxiliary counting signals t t are adequateand therefore properly registered and processed, while the time plotlines bracketed by (b) represent the case where it is assumed that thethird counting signal t (3') is inadequate, i.e., of insutficientamplitude and/or duration, to be considered as a counting signal by thelowest-order counter stage Z The first signal A will appear upon theoccurrence of the first counting signals 1', and the first signal H willappear upon the occurrence of the first auxiliary counting signal I".The new signals T1,7'2 are then formed and are used for controlling thehigher-order counter stages. As explained above and as is apparent fromFIGURES 9a and 9b, the new counting signal 1- is derived from the signalK and the signal H while the new auxiliary counting signal 7 is derivedfrom the signal A and the signal E There will be a time gap between thesignals T1, 1- The time plot further shows that the signal A of the nexthigher-order counter stage is not put out until there is a signal T1.The main store which produces this signal A is thus set with theappearance of a signal 7 Only thereafter can the auxiliary store of thiscounter stage, which produces the signal H be set, and this occurs uponappearance of a signal '1 In the time plot as shown in FIGURE 12, thefirst signal 7 has no effect on the counting operation, because onlyafter the signal A has been formed can a signal 1- produce a signal HThe time plots shown in the lines bracketed by (b) are identical up tothe point represented by the vertical dashed line, which passes throughthe third counting signal 3 and which, as set forth above, is a signalwhich is inadequate for purposes of being treated as a counting signalby the lowest-order counter stage. As a result, the third countingsignal t identified at 3, produces no signal A in consequence of whichno signal H will appear upon the occurrence of the following t -signal3". The signal A will, in fact, not appear until the application of thefourth t -counting signal 4', so that the next H -signal will not appearuntil the application of the next auxiliary counting signal t this beingthe auxiliary counting signal identified at 4".

A comparison between the lines bracketed by (a) and (b) will show that,in case (a), the count of the counter will, upon the application of thefourth t -signal, be four, while in case (b), where the third countingsignal 3' had no eflect, the count of the counter will be only three.

It will thus be seen that, in accordance with the present invention,there is provided a counter responsive to timely displaced countingsignals and auxiliary counting signals t t which counter comprises aplurality of identical or non-identical counter stages each having amain store and an auxiliary store, each of which stores is provided withinput means for receiving counting signals and auxiliary countingsignals. Means are provided for applying the counting signals andauxiliary counting signals t t only to the main store and auxiliarystore, respectively, of the lowest-order counter stage, and for derivingnew counting signals and auxiliary counting signals 1- 7' from theoutputs of the main and auxiliary stores of the lowestorder counterstage. These new counting signals and auxiliary counting signals arethen applied in parallel to the main and auxiliary stores, respectively,of all higher-order counter stages. As is apparent from FIGURES 9a and9b, the new counting signals 7' are derived in logic circuits having thefollowing logic functions:

It will be understood that the above description of the presentinvention is susceptible to various modifications, changes andadaptations, and the same are intended to be comprehended within themeaning and range of equivalents of the appended claims.

, What is claimed is:

1. A static counter responsive to timely displaced counting signals andauxiliary counting signals t t said counter comprising, in combination:

(a) a plurality of counter stages each having a main store and anauxiliary store, each of said stores being provided with input means forreceiving counting signals and auxiliary counting signals;

(b) means for applying the counting signals and auxiliary countingsignals r r only to the main store and auxiliary store, respectively, ofthe lowest-order counter stage;

(0) means for deriving new counting signals and auxiliary countingsignals 1- T2, from the outputs of said main and auxiliary stores ofsaid lowest-order counter stage; and

(d) means for applying said new counting signals and auxiliary countingT1, T2 in parallel to the main and auxiliary stores, respectively, ofall higher-order counter stages.

2. A counter as defined in claim 1 in which T1:(ZO&HO) and =(A &Hwherein A and K are the output and negated output signals of said mainstore of said lowest-order counter stage and H and i are the output andnegated output signals of said auxiliary store of said lowest-ordercounter stage.

3'. A counter as defined in claim 1 wherein said counter stages arenon-identical.

4. A counter as defined in claim 1 wherein said counter stages areidentical.

References Cited UNITED STATES PATENTS 3,218,532 11/1965 Toscano 31828ARTHUR GAUSS, Primary Examiner.

STANLEY MILLER, 1a., Assistant Examiner.

